Jon Y reframes a common technological assumption: that artificial intelligence will inevitably automate every corner of engineering. While the industry fixates on digital logic, Y argues that the analog components—the tiny, invisible bridges between our digital chips and the physical world—remain stubbornly resistant to automation, not because of a lack of computing power, but because the design process is fundamentally an art form rooted in intuition rather than rigid rules.
The Hidden Bottleneck
Y begins by dismantling the idea that digital dominance means analog is obsolete. "Almost every integrated circuit will have an analog component," he notes, pointing out a paradox: "That component is often pretty small. Sometimes as little as 3% of the total thing. Yet this tiny little piece of analog circuitry regularly takes up over half of the integrated circuit's total design cost." This statistic is the piece's anchor. It suggests that while we marvel at the billions of transistors in a smartphone, the real engineering bottleneck lies in the mere hundreds of components that handle the messy reality of the physical world.
The author's framing of analog design as a "goshdarn art" is deliberate. He writes, "Hand-drawn by a chip-Michelangelo staring up at the ceiling night after night." This metaphor is not just colorful; it highlights the core difficulty. Unlike digital design, where transistors are uniform and interactions are predictable, analog circuits are highly sensitive to their environment. Y explains that "parasitic resistance and capacitance are like taxes - unavoidable but very much unwanted." These invisible forces degrade performance, and calculating them requires a level of nuance that current algorithms struggle to replicate.
Analog chip design is a goshdarn art. Hand-drawn by a chip-Michelangelo staring up at the ceiling night after night.
Critics might argue that labeling a process as "art" is a convenient excuse for a lack of tooling maturity. However, Y's analysis of the physics suggests otherwise. The sensitivity of these circuits to minute changes in layout or material properties creates a design space that is "galaxy-sized," making brute-force computational approaches ineffective without human intuition to guide them.
The Physics of Scaling
The commentary takes a sharp turn into the specific challenges of modern manufacturing. As chips shrink to 7 nanometers and below, the problems for analog designers intensify. Y details how "parasitic resistance levels worsen with every new node," creating a scenario where the very technology that powers digital speed becomes a liability for analog precision. He illustrates this with a stark example: "Cutting the metal pitch from 80 nanometers to 48 nanometers - a 40% reduction - raises the line resistance by 6 times."
This is where the argument becomes critical for the semiconductor industry. The executive branch and private sector often focus on process node leadership as the primary metric of success. Yet, Y points out that "every SOC has to have an analog component and it is becoming a big bottleneck in the design." If the analog front-end cannot keep pace with the digital back-end, the entire system's performance is capped. The author's personal anecdote about his father, who designed chips with "paper, a ruler, and a pencil," underscores the depth of human expertise required. "Analog chip design never got automated," his father noted, "and because of that he was lucky, because a lot of designers in other parts of the industry lost their jobs."
The AI Promise and Its Limits
Y then pivots to the potential of machine learning, acknowledging that AI has conquered complex games like Go. He asks, "Now what about analog chip design?" He highlights emerging startups like Astrus.ai and open-source projects like ALIGN and MAGICAL, which attempt to use neural networks to automate layout. "ALIGN - which stands Analog Layout, Intelligently Generated from Netlists - uses a combination of imposed constraints and machine learning models to route and place devices in 24 hours without a human in the loop."
However, Y remains skeptical about a full takeover. He identifies two structural barriers: the proprietary nature of foundry design rules and the immense cost of training data. "The foundry has a set of design rules as part of a Process Design Kit, and that PDK tends to be proprietary. That doesn't jive with open source," he writes. Furthermore, the computational resources required to train models on industrial-scale designs are prohibitive for many. The industry's preference for manual control persists because, as Y puts it, "Designers don't manually draw anything but instead lay out several high-level principles" only when they can trust the output, which they currently cannot.
The complexity of analog chip design helped put food on my family's table... He was lucky, because a lot of designers in other parts of the industry lost their jobs.
Bottom Line
Jon Y's analysis is a necessary correction to the hype surrounding AI in hardware, reminding us that some engineering problems are defined by physical nuance rather than computational volume. The strongest part of his argument is the demonstration that analog design is not just a legacy problem but a growing bottleneck that scales poorly with Moore's Law. The biggest vulnerability in the current AI approach is the lack of access to the proprietary data required to train models that can navigate the complex, non-linear physics of modern nodes. The industry should watch not for a sudden automation of analog design, but for AI tools that act as high-level assistants to the "chip-Michelangos" who still hold the keys to the physical world.