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Is smic n+3’s metal pitch smaller than Intel 18A’s?

In a landscape dominated by geopolitical headlines, Dylan Patel delivers a rare, granular look at what is actually possible when advanced chip manufacturing meets severe export restrictions. The piece's most startling claim isn't that Chinese firms are stuck in the past, but that they have engineered a workaround so aggressive it rivals Western technology from several years ago—while paying a steep price in efficiency and cost.

The Illusion of Parity

Patel opens by dismantling a simplistic narrative often found in tech reporting: that a smaller number on a spec sheet equals modern capability. He notes that while SMIC's third-generation 7 nm process, known as N+3, achieves a minimum metal pitch of 32.5 nanometers—tighter than the 36 nanometers seen in Intel's latest Panther Lake CPUs—the comparison is deceptive. "The headline is true, but incomplete cherry picked metric," Patel writes, immediately grounding the reader in the reality that density does not equal performance.

Is smic n+3’s metal pitch smaller than Intel 18A’s?

This framing is crucial because it forces a shift from binary thinking (blocked vs. unblocked) to a nuanced understanding of trade-offs. By leveraging deep ultraviolet (DUV) multi-patterning—a technique that requires printing layers multiple times to achieve fine details—SMIC has managed to reach logic densities comparable to TSMC's N6 node. However, Patel points out the hidden toll: "N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control." This is a stark reminder of the physical limits of silicon; you cannot simply bypass decades of equipment innovation without consequence.

Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk.

The argument here holds up because it relies on physical teardown data rather than speculation. Patel's team at SemiAnalysis has built a state-of-the-art lab to verify these claims, moving beyond the theoretical models that often plague industry analysis. Critics might note that focusing solely on the manufacturing node overlooks software optimization or system-level design gains, but Patel anticipates this by examining the entire chip architecture.

The Architecture of Constraints

When analyzing the Kirin 9030 Pro chip inside Huawei's latest devices, Patel reveals how engineers are forced to innovate around scarcity. The die shots show a chip that is nearly identical in total area to its predecessor but packed with more cores and larger caches. "A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint," he explains. This is a masterclass in squeezing value from limited resources, reminiscent of how early semiconductor pioneers maximized yield before modern automation took over.

However, the performance gap remains undeniable. Patel contrasts Huawei's prime core with Apple's efficiency cores, noting that "Apple's low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei's prime core." This disparity highlights the fundamental advantage of leading-edge nodes: they allow designers to run at lower voltages and higher frequencies without burning through power or generating excessive heat.

The author emphasizes that this isn't just about raw speed but about the voltage-frequency curve, a metric that dictates how efficiently a chip operates. "What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes," Patel writes, underscoring that export controls have not stopped innovation but have forced it onto a less efficient path. This reframing is vital for policymakers who might assume sanctions are failing because chips are still being made; in reality, they are succeeding by making those chips prohibitively expensive to produce at scale.

The GPU and NPU: A Mixed Bag

The analysis of the graphics and neural processing units offers a more optimistic view. Patel finds that Huawei's Maleoon 935 GPU represents a significant leap forward, even if it still lags behind current flagships. "The GPU is where Huawei makes its biggest gains," he observes, noting that ray-tracing support has been added and performance has jumped significantly over the previous generation.

Yet, the gap with global leaders remains wide. The chip trails behind newer parts from Qualcomm and MediaTek by a factor of two or three in certain benchmarks. Patel's conclusion is measured: "Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve..." This distinction separates engineering brilliance from industrial parity. It suggests that while Chinese firms can catch up to specific historical milestones, they are running on a treadmill where the finish line keeps moving.

Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path.

This sentence captures the essence of the entire report: resilience is not the same as dominance. The ability to produce a functional chip under sanctions is impressive, but the cost in terms of power efficiency and manufacturing complexity creates a long-term competitive disadvantage.

Bottom Line

Patel's teardown provides the most credible evidence yet that export controls are working exactly as intended—not by halting progress entirely, but by forcing adversaries into an inefficient, high-cost loop. The strongest part of this argument is its refusal to accept marketing spin, relying instead on physical measurement and direct comparison. Its biggest vulnerability lies in the rapid pace of system-level innovation; if Huawei successfully pivots to advanced packaging techniques like LogicFolding to bypass node limitations, the efficiency gap could narrow faster than predicted.

Readers should watch not just for new chip releases, but for changes in manufacturing yields and power consumption metrics, which will reveal whether this high-wire act can be sustained.

Deep Dives

Explore these related deep dives:

  • Semiconductor Manufacturing Handbook Amazon · Better World Books by Hwaiyu Geng

  • Multiple patterning

    This technique explains the specific workaround SMIC uses to achieve advanced node densities without EUV lithography, directly illuminating why their N+3 process incurs higher complexity and cost compared to Intel's 18A.

  • Design optimization

    Understanding this methodology reveals how chipmakers squeeze performance out of older equipment by tightly coupling circuit design with manufacturing constraints, which is the core strategy allowing Huawei to match TSMC N6 density despite export controls.

  • Panther Lake (microprocessor)

    Identifying this specific upcoming Intel CPU generation clarifies the precise benchmark SMIC's N+3 process is being compared against, highlighting the narrow margin where Chinese manufacturing has caught up in metal pitch but not necessarily in overall efficiency.

Sources

Is smic n+3’s metal pitch smaller than Intel 18A’s?

by Dylan Patel · SemiAnalysis · Read full article

Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A.

The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control.

We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack.

This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX.

SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients.

Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC:

This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment.

Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, ...